Embodiments of the invention described herein generally relate to forward error correction (FEC) and, more specifically, to low-density parity-check (LDPC) encoding and decoding for satellite communications.
Forward error correction (FEC) is a method of transmitting redundant information with transmitted data to allow a receiver to reconstruct the data if there is an error in the transmission. At a transmitter, a structured redundancy may be added in the form of some parity bits by encoding the data. This structured redundancy may be exploited at the receiver by decoding to correct any errors introduced during transmission.
Some FEC coding schemes incorporate iterative decoding by a decoder. Turbo codes and low-density parity-check (LDPC) codes are examples of coding schemes that may be iteratively decoded. However, because of the complexity of these coding schemes, there may be significant memory and processing resources integrated into components at the receiver. There is, thus, a need in the art to improve aspects of the performance at the decoder.
One of the challenges in performing very high speed decoding for LDPC codes is moving lots of data in parallel in and out of memory. Because of the structure of the codes, usually all the data to be processed in a single clock cycle is not stored together in memory at the receiver. And so traditional decoders may rearrange the data inside the decoder in an order to facilitate highly parallel decoding. This rearrangement of data can be a tedious process and can add to the complexity and latency of the receiver.